Erasure coding is employed in data centers, for example, to reduce the amount of redundant data required for error correction. However, the encoding and decoding of erasure codes occupies 20-30% of the central processing unit (CPU) power in a mid-range server. Hardware-based accelerators can offload the task from the CPU, but a matrix inversion operation used by the erasure codec is highly complex, which prolongs the decoding latency and limits its throughput. In high-rate erasure codecs, the decoding matrix is large, further complicating the matrix inversion computation, increasing latency, and decreasing throughput.